1. Field of the Invention
The present invention relates to technology about programmable scan chains in integrated circuit design. More particularly, the invention relates to an apparatus with programmable scan chains for multiple chip modules and method for programming the same.
2. Description of Related Art
In designs of application-specific integrated circuits, particularly the designs of circuits with gate-counts up to several millions, a chip is commonly integrated with a design for test (DFT) function to increase production's test efficiency. FIG. 1 illustrates a block diagram of a chip with DFT function. In FIG. 1, the chip 100 includes scan chains 102A, 102B . . . 102N, scan input ports 104A, 104B . . . 104N, and scan output ports 106A, 106B . . . 106N. As shown in the FIG. 1, test patterns are input from the scan input ports 104A, 104B . . . 104N, to the scan chains 102A, 102B . . . 102N, then test results are sent to and output from scan output ports 106A, 106B . . . 106N. The function status of the chip 100 is reported by the test patterns output from the 106A, 106B . . . 106N.
However, in order to reduce the I/O ports for lowering the chip package cost, prior art such as U.S. Pat. No. 6,848,067 provides an apparatus having multi-port scan chain selector, where I/O ports are shared in a circuit. The prior art according to the U.S. Pat. No. 6,848,067 is shown in the FIG. 2. In FIG. 2, a chip 200 includes scan chains 202A, 202B . . . 202N, a scan input port 204 and a scan output port 206. According to U.S. Pat. No. 6,848,067, the apparatus reduces the scan I/O ports required by the DFT function. The multiple scan chains 202A, 202B . . . and 202N share a single scan input port 204 via a scan selector 208 and a single output port 206 via a scan selector 210.
As system-on-chip has become common in integrated circuit design, the DFT function becomes popular in mass production of chips. When a chip delivers more functions, the chip requires more transistors, which means the I/O ports count also increases as a result. The I/O ports required by the DFT function do not account for major part of total I/O ports required by a chip. Thus, the apparatus according to U.S. Pat. No. 6,848,067 does not reduce package cost by providing the circuit sharing I/O ports. On the contrary, the apparatus increases the time to test a chip and results in higher test cost.
In addition, due to inherent restrictions of manufacturing process of digital and analog circuits or concerns to improve chip yield, multi-chip module technology is utilized to integrate several small-size chips in one module. However, the wiring bonding out from the scan I/O ports of the chips integrated in the multi-chip module may be interfered by the physical interconnection of the chips. Therefore, the scan chains of the chips can not be used for chip function tests and lead to incomplete coverage of chip function tests. Such problem has been addressed by providing additional function tests to improve overall test coverage. However, additional tests directly increase the test cost but has not yet delivered test coverage as expected.